Server Structural FEA Engineer

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > Systems Engineering

General Summary

Qualcomm's Data Center team is developing high-performance, energy-efficient server solutions for data center applications. We are looking for highly talented, innovative, and collaborative individuals to contribute to cutting-edge server technology development.

Our Mission

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you will collaborate with world-class engineers to create innovative solutions that advance performance, energy efficiency, scalability, and reliability. Our focus is on developing reference platforms based on Qualcomm Snapdragon SoCs and delivering comprehensive hardware and software solutions, reference designs, user guides, SDKs, and related enablement.

Position Summary

We are seeking a Staff / Senior Staff Server Structural FEA Engineer with deep expertise in semiconductor package mechanics, structural reliability, and advanced finite element analysis. The role focuses on structural integrity and reliability of server SoCs, spanning die- and package-level behavior through interaction with the server platform. The scope includes both soldered and socketed SoC packages and their mechanical interaction with PCBs, sockets and retention systems, cooling solutions, and thermal interface materials, including TIM1.5.

The ideal candidate is a recognized subject matter expert who can develop predictive methodologies, evaluate failure mechanisms, quantify design margins and uncertainty, and translate analysis into actionable package and platform design guidance. The engineer will assess structural behavior across package assembly, system integration, qualification, and operation, with emphasis on chip-package interaction (CPI), warpage, die and interconnect integrity, solder-joint reliability, and mechanically coupled thermal interface risks.

This senior individual contributor will work closely with package engineering, computational modeling, thermal, mechanical, electrical, manufacturing, reliability, and system/platform engineering teams to align assumptions, material properties, boundary conditions, failure criteria, and correlation approaches. The engineer will develop independent analyses where needed and partner with system-level structural FEA engineers to connect SoC/package mechanical behavior to broader platform and lifecycle assessments.

Key Responsibilities

• Develop and apply advanced structural and thermo-mechanical FEA methodologies for server SoCs and advanced semiconductor packages, including CPI, package assembly, warpage, stress, deformation, and structural reliability.
• Evaluate both soldered and socketed packages under package assembly, SMT, socket and retention loading, cooling-system loading, temperature cycling, qualification, and operating conditions.
• Analyze package-to-platform mechanical interaction among the SoC package, PCB, socket or retention system, heatsink or cold plate, and thermal interface materials, including TIM1.5.
• Apply advanced FEA techniques including submodeling, contact analysis, material and geometric nonlinearity, viscoelasticity, creep, fatigue, fracture or damage mechanics, and coupled structural-thermal analysis as appropriate.
• Develop physics-based reliability and life-prediction models for relevant failure mechanisms, including solder and bump fatigue, die and BEOL stress, substrate and interposer cracking, delamination, and creep. Perform BLR and solder-joint reliability analyses to quantify damage accumulation, design margins, and expected life.
• Perform sensitivity, uncertainty, and bounding analyses to identify dominant parameters, quantify structural risk, and guide package and platform architecture decisions before hardware is available.
• Define model-validation and correlation strategies using material characterization, package/board measurements, reliability and qualification testing, manufacturing data, and system-level test results, including development of test vehicles and methods where needed.
• Partner with package engineering and computational modeling teams to align modeling assumptions, material properties, process inputs, boundary conditions, revision control, correlation methodologies, and failure criteria.
• Develop independent analyses, sensitivity studies, or targeted model cross-checks as needed to reconcile differing predictions, quantify uncertainty, and evaluate server-specific package-to-platform boundary conditions.
• Work closely with system/platform structural-analysis engineers to provide package mechanical properties, load limits, deformation behavior, and failure criteria supporting broader platform, system, and rack-level lifecycle analyses.
• Apply expertise in package architectures and substrate technologies, including FCBGA, FCLGA/HFCBGA, chiplet-based designs, HBM integration, 2.5D interposers or bridges, and 3D packaging technologies.
• Develop scalable workflows, automation, modeling standards, best-known methods (BKMs), and validation frameworks. Experience with ANSYS APDL-based workflow development is strongly preferred.
• Translate complex simulation results into clear design requirements and recommendations for cross-functional engineering teams, leadership, customers, and suppliers.

Qualifications

• Master's degree in Mechanical Engineering, Engineering Mechanics, Materials Science, Physics, or a related field.
• 10+ years of advanced FEA experience in semiconductor packaging, microelectronics assembly, CPI, structural reliability, and interconnect technologies.
• Strong foundation in structural and failure mechanics, materials science, thermo-mechanical behavior, fatigue and creep, with experience applying nonlinear FEA techniques including contact, submodeling, thermal cycling, and interconnect reliability analysis.
• Demonstrated experience modeling semiconductor-package failure mechanisms and correlating simulations with experimental, manufacturing, or qualification data.
• Proficiency in ANSYS Workbench, ANSYS APDL, ABAQUS, or equivalent nonlinear FEA tools.
• Proven ability to operate independently and lead in cross-functional environments, with strong technical documentation, communication, and presentation skills.

Preferred Qualifications

• Ph.D. in Mechanical Engineering, Engineering Mechanics, Materials Science, Physics, or a related field.
• Deep expertise in package mechanics, CPI, package assembly simulation, warpage prediction, die and BEOL reliability, and solder or interconnect reliability.
• Demonstrated experience with both soldered and socketed high-pin-count server packages and package interaction with PCBs, sockets, retention hardware, heatsinks or cold plates, and TIM materials.
• Proven experience developing physics-based reliability models and life predictions for solder joints, bumps, die/package structures, substrates, interposers, underfill, adhesives, or related failure mechanisms.
• Proven simulation-to-test correlation using warpage measurements, strain or displacement measurements, material characterization, thermal-cycling data, mechanical loading tests, or qualification results.
• Experience developing APDL automation, reusable workflows, modeling standards, and BKMs.
• Experience with coupled structural-thermal analysis and mechanical/thermal co-optimization.
• Understanding of server and OCP platform designs and associated assembly, handling, transportation, qualification, and operating environments.

Minimum Qualifications

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.

OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits

$190,200.00 - $285,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.