Develop constrained-random, directed, and scenario-based tests.
Integrate third-party VIPs and custom verification IPs.
Assertion & Formal Verification
Develop SystemVerilog Assertions (SVA) for protocol and functional checking.
Utilize assertion-based verification techniques to improve bug detection efficiency.
Collaborate with formal verification teams for property development and closure.
Debug & Root Cause Analysis
Analyze simulation failures and identify RTL, testbench, or architectural issues.
Work closely with design and architecture teams to resolve functional and performance-related bugs.
Lead complex debug activities across multiple IPs and subsystems.
Coverage & Sign-Off
Define and track functional coverage models.
Drive functional, code, assertion, and cross-coverage closure.
Review verification metrics and provide sign-off recommendations.
Ensure compliance with overall project verification and quality goals.
SoC Verification
Lead end-to-end verification of large SoCs including:Interconnect and fabric verificationCache coherency verificationMemory subsystem verificationBoot and reset validationLow-power verificationPerformance and stress testing
Leadership & Mentoring
Provide technical leadership to verification teams.
Mentor junior and senior engineers on UVM, verification methodologies, and debug techniques.
Participate in hiring, technical interviews, and project planning.
Drive best practices and verification process improvements.