Camera ISP System Architecture Engineer, up to Staff

Company

Qualcomm Semiconductor Limited

Job Area

Engineering Group, Engineering Group > Camera Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Camera Engineer you will work on ideas that touch our daily life – creating everlasting connected memories and assist in building innovative devices through human and computer vision technologies in the Mobile, Automotive, XR, IoT & Compute space. You will have limitless opportunities to learn, grow and lead the world of Imaging.

Job Function

Architect and develop advanced Image Signal Processing (ISP) hardware pipelines for high-performance, low-power semiconductor products, enabling industry-leading image quality across IoT, mobile, camera-centric devices, and embedded platforms.

Qualcomm advances Industrial and Embedded IoT innovation, enabling next-generation experiences and a smarter, seamlessly connected world.

We are seeking an experienced ISP Design Engineer to architect and develop high-performance, low-power ISP hardware pipelines. You will define microarchitectures, build performance and accuracy models, implement datapaths, optimize PPA, and validate ISP functions across mobile, IoT, camera-centric, and embedded products.

You will collaborate with imaging algorithm, system architecture, RTL, physical design, firmware, and verification teams to deliver advanced camera and computer vision capabilities.

This role requires a solid understanding of imaging algorithms and ASIC design to translate image-quality requirements into efficient, production-ready ISP architectures.

Responsibilities

• Architect, design, and optimize ISP ASIC hardware modules for conventional and AI-based imaging algorithms.

• Translate imaging and image-quality requirements into efficient microarchitectures and datapaths, balancing image quality, throughput, latency, bandwidth, power, and area.

• Partner with imaging and AI algorithm teams to translate algorithms into hardware-efficient architectures and define implementation constraints and trade-offs.

• Develop C/C++ or SystemC models for architecture exploration, functional validation, performance analysis, and RTL or silicon correlation.

• Participate in architecture and RTL design reviews, identify implementation risks, and provide actionable recommendations.

• Collaborate with verification, physical design, firmware, and system teams to achieve functional, performance, and PPA targets throughout the silicon development lifecycle.

• Support silicon bring-up, debugging, tuning, and correlation against pre-silicon models and image-quality targets.

• Be available for business travel across APAC and China.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Solid understanding of image signal processing fundamentals, including ISP pipelines, noise reduction, HDR, color processing, image enhancement, and image-quality evaluation.

• Hands-on ASIC/RTL design and implementation experience with strong knowledge of Verilog/System Verilog, microarchitecture, and data path design.

• Proficiency in C/C++ for modeling, simulation, validation, and performance analysis.

• Understanding of conventional and AI-based imaging algorithms, including their dataflow, computational complexity, numerical precision, and hardware implementation considerations.

• Knowledge of SoC architecture, memory hierarchy, bandwidth analysis, and low-power design techniques.

• Ability to review architecture and RTL designs, identify technical risks, and evaluate image quality, performance, bandwidth, power, and area trade-offs.

• Strong problem-solving and communication skills, with the ability to drive technical discussions across algorithm, hardware, software, and system teams.

Preferred Qualifications

• Hands-on experience in ISP, computational photography, computer vision, or AI imaging system development.

• Experience taking an imaging hardware design from architecture definition and RTL implementation through verification and silicon bring-up.

• Familiarity with camera systems, sensor pipelines, 3A (AWB/AEC/AF), and image-quality tuning.

• Familiarity with SystemC, Python, or FPGA development flows.

• Familiarity with PyTorch or TensorFlow and AI model optimization techniques, including quantization, PTQ/QAT, and fixed-point conversion.

• Product development experience in mobile, edge AI, automotive, surveillance, or camera-centric applications.

Keywords

ISP Architecture, Image Processing, Computational Photography, ASIC, RTL, Verilog, System Verilog, Microarchitecture, Datapath Design, C/C++, System C, PPA, Image Quality Evaluation, AI Imaging, FPGA

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.

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